Welcome！[Sign In] ！[Sign Up]！
Front-page it | Collect it | [中国-简体中文]
FAQ Fav
Location:
Search - stopwatch vhdl

Search list

[VHDL-FPGA-Verilog] vhdl-多功能电子表

Description: 这是一个用vhdl编的多功能电子秒表，可以记录几个人的时间，并且可以在跑秒的时候查看记录。。〔原创〕-This is a series with VHDL multifunctional electronic stopwatch, can be recorded by several people, and that they could run in the second examined the records. . [Original]
Platform: | Size: 5120 | Author: 王继东 | Hits:

[VHDL-FPGA-Verilog] byvhdstopwatchl

Description: 1.高精度数字秒表（0.01秒的vhdl语言实现） 2.具有定时，暂停，按键随机存储，翻页回放功能； 3.对30M时钟分频产生显示扫描时钟 4.精度高达0.01s,并且可以通过改变主频来更改分频比和记数间隔，可控性高。 5.模块化设计，其中的许多函数可以成为vhdl语言的通用经典例子（包含分频电路设计，动态扫描时钟设计，译码电路设计，存储器设计，存储回放显示设计）-1. High-precision digital stopwatch (0.01 seconds vhdl language) 2. With a timer, suspended Random memory keys, flip playback function; 3. right 30M clock frequency scan have revealed four clock. Precision high 0.01s and and can be changed to alter the frequency than the frequency interval and Hutchison, controlled high. 5. Modular design, Many of these functions can become the common language vhdl classic examples (including sub-frequency circuit design, Dynamic scanning clock design, decoding circuit design, memory design, storage intervals showed Design)
Platform: | Size: 2048 | Author: 方周 | Hits:

[Documents] VHDL

Description: VHD设计实例8位加法器的设计分频电路数字秒表的设计-VHD Design 8 adder design of sub-frequency circuit design of digital stopwatch
Platform: | Size: 569344 | Author: yyy | Hits:

[Software Engineering] clock

Description: 基于vhdl的数字钟 有闹钟,秒表,时钟,日期等功能 秒表可以开始,暂停,清零, 时钟可以设置时间, 还可以设置日期-VHDL based on the digital clock has an alarm clock, stopwatch, clock, date, stopwatch functions can start, pause, cleared, the clock can be set-up times, you can set the date
Platform: | Size: 3072 | Author: 张廷 | Hits:

[VHDL-FPGA-Verilog] watch

Description: vhdl语言编写的一个秒表源码，包括在LCD上显示的部分，附带TB源码，对初学者比较实用-VHDL language, a stopwatch source, including the LCD display part, incidental TB source, more practical for beginners
Platform: | Size: 98304 | Author: ronniy | Hits:

[Other] C2

Description: 功能更加完善的基于vhdl的数字时钟设计 有秒表，时钟，时期，闹钟的功能和整点报时，时间调整，日期调整，闹钟的设定 、、、、、、、 秒表有开始，暂停，清零等功能，且只有在暂停的情况下才能清零。-Function more complete VHDL-based design of the digital clock stopwatch, clock, time, alarm clock function and the whole point timekeeping, time adjustment, date, alarm clock settings ,,,,,,, stopwatch has started, pause, Clear and other functions, and only in the case of the suspension can be cleared.
Platform: | Size: 817152 | Author: 张廷 | Hits:

[VHDL-FPGA-Verilog] stop_watch

Description: 采用Quartus2编写的电子秒表电路 实现计时、暂停等功能-Quartus2 prepared using electronic stopwatch timer circuit, suspension and other functions
Platform: | Size: 349184 | Author: gz208 | Hits:

[assembly language] dig-clock

Description: 数字钟，定时亮灯，可作秒表，有年月日显示-Digital clock, timing lights, can be used for stopwatch, date display has
Platform: | Size: 19442688 | Author: 钱慕君 | Hits:

[VHDL-FPGA-Verilog] stopwatch

Description: 电子秒表，可以显示0.01S到59’59”99.带有开始、暂停、复位于一键的控制功能。-Electronic stopwatch, can display 0.01S to 59 59 99. With a moratorium, rehabilitation located in a key control functions.
Platform: | Size: 1024 | Author: jacky | Hits:

[VHDL-FPGA-Verilog] secondwatch

Description: 用VERILOG实现的秒表 用VERILOG实现的秒表-Realized by Verilog Verilog achieved using a stopwatch stopwatch
Platform: | Size: 393216 | Author: wwyjs163 | Hits:

[VHDL-FPGA-Verilog] clock

Description: 数字秒表的设计，reset为归零设置，start为重新计时设置-Design of digital stopwatch, reset to zero settings, start time set for the re-
Platform: | Size: 309248 | Author: zhang | Hits:

[VHDL-FPGA-Verilog] VHDL_MIAOBIAO_CODE

Description: 基于CYCLONE系列FPGA EP1C3T144C8的VHDL秒表代码-CYCLONE series based on the FPGA EP1C3T144C8 stopwatch VHDL code
Platform: | Size: 422912 | Author: 沈世荣 | Hits:

[VHDL-FPGA-Verilog] stopwatch

Description: 秒表可计时，用VHDL编译的源代码，从0.1到60秒计时，解压后直接用Quartus打开project即可-Stopwatch timer can be used to compile the VHDL source code, from 0.1 to 60 seconds from time, after extracting the direct use of Quartus can open the project
Platform: | Size: 577536 | Author: xie | Hits:

[Documents] vhdl

Description: 6位LED电子钟,非常实用实做过实验，自动报时，秒表-6 LED electronic clock, very useful experiment is done, automatic timer, stopwatch. . .
Platform: | Size: 4096 | Author: 王睿 | Hits:

[VHDL-FPGA-Verilog] stopwatch

Description: VHDL语言设计的秒表，实现计时功能，实现报时功能，并且通过硬件实验。-VHDL language design stopwatch, timer function of the realization, the realization of time functions, and through hardware experiments.
Platform: | Size: 1647616 | Author: 王蕊 | Hits:

[VHDL-FPGA-Verilog] stopwatch

Description: Quartus II工程压缩文件，是一个典型的基于FPGA的秒表工程项目，有50MHz分频、计数、译码等模块。采用VHDL语言编写。-Quartus II project files, is a typical FPGA-based project of the stopwatch, a 50MHz frequency, counting, decoding modules. Using VHDL language.
Platform: | Size: 464896 | Author: kg21kg | Hits:

[VHDL-FPGA-Verilog] StopWatch

Description: Verilog 编写的 秒表程序，在数码管上显示，带有清0和暂停键-Stopwatch Implemented by Verilog hdl
Platform: | Size: 584704 | Author: 洪磊 | Hits:

[VHDL-FPGA-Verilog] stopwatch

Description: 基于vhdl的数字秒表，计时精度为1/100秒，最长计时时间为59分59.59秒；设有复位开关、起停开关；验证可用。-On vhdl digital stopwatch, timing accuracy of 1/100 seconds, the longest time time of 59 minutes 59.59 seconds with reset switch, start-stop switches validation is available.
Platform: | Size: 266240 | Author: ly | Hits:

[VHDL-FPGA-Verilog] stopwatch

Description: 数字秒表的VHDL代码。当设计文件加载到目标器件后，设计的数字秒表从00-00-00开始计秒。，直到按下停止按键（按键开关S2）。数码管停止计秒。按下开始按键（按键开关S1），数码管继续进行计秒。按下复位按键（核心板上复位键）秒表从00-00-00重新开始计秒。-The VHDL code for digital stopwatch. When the design document loaded into the target device, the designed digital stopwatch count the seconds from the 00-00-00. Until you press stop key (key switch S2). Nixie tube stop count seconds. Press the start button (key switch S1), the digital control continue to count seconds. Press the reset button (core panel reset button) to restart the stopwatch count seconds from the 00-00-00.
Platform: | Size: 1024 | Author: 王唐小菲 | Hits:

[VHDL-FPGA-Verilog] STOPWATCH

Description: 是基于FPGA/CPLD的跑表程序，可以存储记录多个运动员的跑步时间，是利用VHDL语言编写的，可以有助于学习EDA技术，可以参考学习，可以帮助你完成VHDL语言的课程设计。-Is based on FPGA/CPLD s stopwatch program, many athletes can store records of running time, is the use of VHDL language, and can help to learn EDA, can refer to the study, can help you complete VHDL language curriculum design.
Platform: | Size: 661504 | Author: 王亮 | Hits:
« 12 3 4 5 6 7 8 9 10 »

CodeBus www.codebus.net